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SPLC783A
16COM/80SEG Controller/Driver
MAR. 10, 2005 Version 1.4
Sunplus Technology reserves the right to change this documentation without prior notice. Information provided by Sunplus Technology is believed to be accurate and reliable. However, Sunplus Technology makes no warranty for any errors which may appear in this document. Contact Sunplus Technology to obtain the latest version of device specifications before placing your order. No responsibility is assumed by Sunplus Technology for any infringement of
patent or other rights of third parties which may result from its use. In addition, Sunplus products are not authorized for use as critical components in life support devices/ systems or aviation devices/systems, where a malfunction or failure of the product may reasonably be expected to result in significant injury to the user, without the express written approval of Sunplus.
SPLC783A
Table of Contents
PAGE
1. GENERAL DESCRIPTION .......................................................................................................................................................................... 4 2. BLOCK DIAGRAM ...................................................................................................................................................................................... 4 3. FEATURES .................................................................................................................................................................................................. 4 4. SIGNAL DESCRIPTIONS............................................................................................................................................................................ 5 4.1. PIN MAP ............................................................................................................................................................................................... 6 5. FUNCTIONAL DESCRIPTIONS.................................................................................................................................................................. 7 5.1. OSCILLATOR .......................................................................................................................................................................................... 7 5.2. CONTROL AND DISPLAY INSTRUCTIONS ................................................................................................................................................... 7 5.3. INSTRUCTION TABLE............................................................................................................................................................................... 9 5.4. 8-BIT OPERATION AND 8-DIGIT 1-LINE DISPLAY (USING INTERNAL RESET).............................................................................................. 10
5.5. 4-BIT OPERATION AND 8-DIGIT 1-LINE DISPLAY (USING INTERNAL RESET)...............................................................................................11 5.6. 8-BIT OPERATION AND 8-DIGIT 2-LINE DISPLAY (USING INTERNAL RESET)...............................................................................................11 5.7. RESET FUNCTION............................................................................................................................................................................... 12 5.8. DISPLAY DATA RAM (DD RAM)............................................................................................................................................................ 14 5.9. TIMING GENERATION CIRCUIT............................................................................................................................................................... 14 5.10. LCD DRIVER CIRCUIT ....................................................................................................................................................................... 14 5.11. CHARACTER GENERATOR ROM (CG ROM)....................................................................................................................................... 14 5.12. CHARACTER GENERATOR RAM (CG RAM)........................................................................................................................................ 14 5.13. CURSOR/BLINK CONTROL CIRCUIT .................................................................................................................................................... 18 5.14. INTERFACING TO MPU....................................................................................................................................................................... 19 5.15. SUPPLY VOLTAGE FOR LCD DRIVE..................................................................................................................................................... 20 5.16. REGISTER --- IR (INSTRUCTION REGISTER) AND DR (DATA REGISTER) ............................................................................................. 23 5.17. BUSY FLAG (BF) ............................................................................................................................................................................... 23 5.18. ADDRESS COUNTER (AC).................................................................................................................................................................. 23 5.19. I/O PORT CONFIGURATION ................................................................................................................................................................ 23 6. ELECTRICAL SPECIFICATIONS ............................................................................................................................................................. 24 6.1. ABSOLUTE MAXIMUM RATINGS ............................................................................................................................................................. 24 6.2. DC CHARACTERISTICS (VDD = 2.7V TO 4.5V, TA = 25) ..................................................................................................................... 24 6.3. AC CHARACTERISTICS (VDD = 2.7V TO 4.5V, TA = 25) ..................................................................................................................... 25 6.4. DC CHARACTERISTICS (VDD = 4.5V TO 5.5V, TA = 25)..................................................................................................................... 26 6.5. AC CHARACTERISTICS (VDD = 4.5V TO 5.5V, TA = 25) ..................................................................................................................... 26 7. APPLICATION CIRCUITS ......................................................................................................................................................................... 29 7.1. R-OSCILLATOR .................................................................................................................................................................................... 29 7.2. INTERFACE TO MPU............................................................................................................................................................................. 29 7.3. SPLC783A APPLICATION CIRCUIT ........................................................................................................................................................ 30 7.4. APPLICATIONS FOR LCD ...................................................................................................................................................................... 30 8. CHARACTER GENERATOR ROM ........................................................................................................................................................... 33 8.1. SPLC783A - 001 ................................................................................................................................................................................ 33 8.2. SPLC783A - 003 ................................................................................................................................................................................ 34
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9. PACKAGE/PAD LOCATIONS ................................................................................................................................................................... 35 9.1. PAD ASSIGNMENT AND LOCATIONS....................................................................................................................................................... 35 9.2. PACKAGE INFORMATION ....................................................................................................................................................................... 35 9.3. ORDERING INFORMATION ..................................................................................................................................................................... 35 9.4. STORAGE CONDITION AND PERIOD FOR PACKAGE ................................................................................................................................. 36 9.5. RECOMMENDED SMT TEMPERATURE PROFILE...................................................................................................................................... 36 10. DISCLAIMER............................................................................................................................................................................................. 37 11. REVISION HISTORY ................................................................................................................................................................................. 38
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SPLC783A
16COM/80SEG CONTROLLER/DRIVER
1. GENERAL DESCRIPTION
The SPLC783A, a dot-matrix LCD controller and driver from SUNPLUS, is a unique design for displaying alpha-numeric, Japanese-Kana characters and symbols. The SPLC783A A single By provides two types of interfaces to MPU: 4-bit and 8-bit interfaces. The transferring speed of 8-bit is twice faster than 4-bit. SPLC783A is able to display up to two 16-character lines. be extended. rank.
3. FEATURES
Character generator ROM: 10880 bits Character font 5 x 8 dots: 192 characters Character font 5 x 10 dots: 64 characters Character generator RAM: 512 bits Character font 5 x 8 dots: 8 characters Character font 5 x 10 dots: 4 characters 4-bit or 8-bit MPU interfaces
cascading with SPLC100 or SPLC063, the display capability can The CMOS technology ensures the power saves in the most efficient way and the performance keeps in the highest
Direct driver for LCD: 16 COMs x 80 SEGs Duty factor (selected by program): 1/8 duty: 1 line of 5 x 8 dots 1/11 duty: 1 line of 5 x 10 dots
2. BLOCK DIAGRAM
OSC1 OSC2 VDD VSS
Timing Generation Circuit
Parallel to Serial Data Conversion Circuit 5 5 Busy Flag Character Generator ROM 8 Character Generator RAM 8
DB0-DB3 DB4-DB7 RS R/W E Power Supply for LCD Drive : (V1-V5) I/O Buffer 8 8
Data Register
Instruction Register
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1/16 duty: 2 lines of 5 x 8 dots / line Built-in power on automatic reset circuit Support external clock operation Low Power Consumption
CLK1, CLK2 M 80-bit Cursor Blink Control Circuit Shift Register D 80
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Built-in oscillator circuit (with external resistor)
Package form: bare chip available
Latch Circuit
80
8
7
7
8
Display Data RAM 80 Bytes
16-bit Shift
16
80 Segments x 16 Commons LCD Driver
COM1COM16
Instruction Decorder 7
Register
7
SEG1SEG80
Address Counter
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4. SIGNAL DESCRIPTIONS
Mnemonic VDD VSS OSC1 OSC2 V1 - V5 E R/W RS PIN No. 49 34 36 35 37 - 41 48 47 46 I I I I Type I I Power input Ground Both OSC1 and OSC2 are connected to resistor for internal oscillator circuit. For external clock operation, the clock is input to OSC1. Supply voltage for LCD driving. A start signal for reading or writing data. A signal for selecting read or write actions. 1: Read, 0: Write. A signal for selecting registers. 1: Data Register (for read and write) 0: Instruction Register (for write), DB0 - DB3 DB4 - DB7 CLK1 CLK2 M D SEG1 - SEG33 50 - 53 54 - 57 42 43 44 45 I/O I/O O O O O Low 4-bit data Description
SEG34 - SEG80 COM1 - COM16 TEST
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High 4-bit data Clock to latch serial data D. Clock to shift serial data D. Switch signal to convert LCD waveform to AC. 1: Selection, 0: Non-selection. Segment signals for LCD. 33 - 1 O 121 - 75 59 - 74 58 O I Common signals for LCD. TEST pin. This pin must be fixed to VDD or open.
Busy flag - Address Counter (for read).
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Sends character pattern data corresponding to each common signal serially.
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4.1. PIN Map
SEG34
128
SEG35
127
SEG36
126
SEG37
125
SEG38
124
SEG39
123
SEG40
122
SEG41
121
SEG42
120
SEG43
119
SEG44
118
SEG45
117
SEG46
116
SEG47
115
SEG48
114
SEG49
113
SEG50
112
SEG51
111
SEG52
110
SEG53
109
SEG54
108
SEG55
107
SEG56
106
SEG57
105
SEG58
104
SEG59
103
NC SEG33 SEG32 SEG31 SEG30 SEG29 SEG28 SEG27 SEG26 SEG25 SEG24 SEG23 SEG22 SEG21 SEG20 SEG19 SEG18 SEG17 SEG16 SEG15 SEG14 SEG13 SEG12 SEG11 SEG10 SEG9 SEG8 SEG7 SEG6 SEG5 SEG4 SEG3 SEG2 SEG1 VSS OSC2 OSC1 NC
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38
102 101 100
SEG60 SEG61 SEG62 SEG63
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39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64
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99 98 97 96 95
O
94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65
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SEG65 SEG66 SEG67 SEG68 SEG69 SEG70 SEG71 SEG72 SEG73 SEG74 SEG75 SEG76 SEG77 SEG78 SEG79 SEG80 COM16 COM15 COM14 COM13 COM12 COM11 COM10 COM9 COM8 COM7 COM6 COM5 COM4 COM3 COM2 COM1 NC
SEG64
TEST
NC
DB7
DB6
DB5
DB4
DB3
DB2
DB1
DB0
VDD
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NC
NC
NC
V1
V2
V3
V4
V5
CLK1
CLK2
M
D
RS
R/W
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5. FUNCTIONAL DESCRIPTIONS
5.1. Oscillator
SPLC783A oscillator supports not only the internal oscillator operation, but also the external clock operation. S=1 S=1 I/D=1 I/D=0 It shifts the display to the left It shifts the display to the right
5.2. Control and Display Instructions
Control and display instructions are described in details as follows:
5.2.4. Display ON/OFF control
RS R/W DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 0 0 0 0
5.2.1. Clear display
RS Code 0 R/W DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 0 0 0 0 0 0 0 0 1
Code
0
D = 1: Display on, D = 0: Display off C = 1: Cursor on, C = 0: Cursor off B = 1: Blinks on, B= 0: Blinks off
It clears the entire display and sets Display Data RAM Address 0 in Address Counter.
5.2.2. Return home
RS Code 0
R/W DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 0 0 0 0 0 0 0 1 X
X: Do not care (0 or 1)
It sets Display Data RAM Address 0 in Address Counter and the display returns to its original position. displayed). change. The cursor or blink goes to the most-left side of the display (to the 1st line if 2 lines are The contents of the Display Data RAM do not
5.2.3. Entry mode set
and shifts the display.
RS Code 0
During writing and reading data, it defines cursor moving direction
R/W DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 0 0 0 0 0 0 1 I/D S
I / D = 1: Increment, I / D = 0: Decrement.
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5 x 8 dot character font 8th line Cursor
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1
D
C
B
5 x 10 dot
character font
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11th line
5.2.5. Cursor or display shift
display.
Without changing DD RAM data, it moves cursor and shifts
RS 0
R/W DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 0 0 0 0 1 S/C R/L X X
Code
Blink display alternately
S = 1: The display shift, S = 0: The display does not shift.
S/C 0 0 1 1
R/L 0 1 0 1 Shift cursor to the left Shift cursor to the right Shift display to the left. Shift display to the right.
Description
Address Counter AC = AC - 1 AC = AC + 1
Cursor follows the display shift Cursor follows the display shift
AC = AC AC = AC
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5.2.6. Function set
RS Code 0 R/W DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 0 0 0 1 DL N F X X
Display data RAM can be read or written after this setting. In one-line display (N = 0), (aaaaaaa)2: (00)16 - (4F)16. In two-line display (N = 1), (aaaaaaa)2: (00)16 - (27)16 for the first line, (aaaaaaa)2: (40)16 - (67)16 for the second line.
X: Do not care (0 or 1) DL: It sets interface data length. DL = 1: Data transferred with 8-bit length (DB7 - 0). DL = 0: Data transferred with 4-bit length (DB7 - 4). It requires two times to accomplish data transferring. N: It sets the number of the display line. N = 0: One-line display. N = 1: Two-line display. F: It sets the character font. F = 0: 5 x 8 dots character font. F = 1: 5 x 10 dots character font.
Code RS 0
5.2.9. Read busy flag and address
R/W DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 1
N 0 0 1
F 0 1 X
No. of Display Lines 1 1 2
It cannot display two lines with 5 x 10 dots character font.
5.2.7. Set character generator RAM address
RS Code 0
R/W DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 0 0 1 a a a a a a
It sets Character Generator RAM Address (aaaaaa)2 to the Address Counter.
Character Generator RAM data can be read or written after this setting.
5.2.8. Set display data RAM address
RS Code 0
R/W DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 0 1 a a a a a a a
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Character Font Duty Factor 5 x 8 dots 1/8 5 x 10 dots 5 x 8 dots 1 / 11 1 / 16
When BF = 1, it indicates the system is busy now and it will not accept any instruction until not busy (BF = 0). At the same time, the content of Address Counter (aaaaaaa)2 is read.
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5.2.10. Write data to character generator RAM or display data RAM
RS 1
R/W DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 0 d d d d d
Code
It writes data (dddddddd)2 to character generator RAM or display
data RAM.
5.2.11. Read data from character generator RAM or display data RAM
RS 1
R/W DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 1 d d d d d d d d
Code
It reads data (dddddddd)2 from character generator RAM or display data RAM.
It sets Display Data RAM Address (aaaaaaa)2 to the Address Counter. To read data correctly, do the following: 1). The address of the Character Generator RAM or Display Data RAM or shift the cursor instruction. 2). The " Read " instruction.
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5.3. Instruction Table
Instruction Code Instruction RS R/W DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 Description Execution time Fosc= 190KHz Write "20H" to DDRAM Clear Display 0 0 0 0 0 0 0 0 0 1 and set DDRAM address to "00H" from AC Set DDRAM address to "00H" Return Home 0 0 0 0 0 0 0 0 1 return from cursor AC to and its 2.16ms 1.52ms 1.18ms Fosc= 270KHz Fosc= 350KHz
original position if shifted. The contents of DDRAM are not changed. Assign cursor
Entry Mode Set
Display ON/ OFF Control
Cursor or Display Shift
Function Set
Set CGRAM Address Set DDRAM Address
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0 0 0 0 0 0 0 1 I/D S direction and enable the shift of entire display Set display 53s (D), 0 0 0 0 0 0 1 D C B cursor(C), and blinking of cursor(B) on/off control bit. 53s Set cursor moving and display shift control bit, and the direction, without changing data. of 0 0 0 0 0 1 S/C R/L 53s DDRAM Set interface data length (DL: 8-bit/4-bit), numbers display line (N: 0 0 0 0 1 DL N F of 53s 2-line/1-line) and, display font type (F:5x10 dots/5x8 dots) 0 0 0 0 0 1 1 AC5 AC4 AC3 AC2 AC1 AC0 Set CGRAM address in address counter. address counter 53s 53s AC6 AC5 AC4 AC3 AC2 AC1 AC0 Set DDRAM address in Whether during internal operation or not can be The contents of address counter read. can also be 0 1 BF AC6 AC5 AC4 AC3 AC2 AC1 AC0 known by reading BF. 1 1 0 1 D7 D7 D6 D6 D5 D5 D4 D4 D3 D3 D2 D2 D1 D1 D0 D0 Write data into internal RAM (DDRAM/CGRAM). Read data from internal RAM (DDRAM/CGRAM). 53s 53s
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1.52ms
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1.18ms 29s 29s
29s
38s
29s
38s 38s
29s 29s
Read Busy Flag and Address Counter
Write Data to RAM Read Data from RAM
Note: "-": don't care
38s 38s
29s 29s
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5.4. 8-Bit Operation and 8-Digit 1-Line Display (Using Internal Reset)
No. 1 2 Instruction Power on. (SPLC783A starts initializing) Function set
RS R/W DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 0 0 0 0 1 1 0 0 X X
Display Power on reset. No display.
Operation
Set to 8-bit operation and select 1-line display line and character font.
3
Display on / off control
0 0 0 0 0 0 1 1 1 0
_
Display on. Cursor appear. Increase address by one.
4
Entry mode set
0 0 0 0 0 0 0 1 1 0
_
It will shift the cursor to the right when writing to the DD RAM/CG RAM. Now the display has no shift. Write " W ".
5
Write data to CG RAM / DD RAM
1 0 0 1 0 1 0 1 1 1
W_
The cursor is incremented by one and shifted to the right. Write " E ".
6
Write data to CG RAM / DD RAM
1 0 0 1 0 0 0 1
7 8
Write data to CG RAM / DD RAM
1 0 0 1 0 0 0 1
9
Entry mode set
0 0 0 0
10
Write data to CG RAM / DD RAM
1 0 0 0 1 0 0 0
11
Write data to CG RAM / DD RAM
1 0 0 1 0 0 0 0
12 13
1 0 0
Write data to CG RAM / DD RAM
1 0 1 1 0
14
Cursor or display shift
0 0 0 0 0
15
Cursor or display shift
0 0 0 0 0
16
Write data to CG RAM / DD RAM
1 0 0 1 0 0 1 1
17
Cursor or display shift
0 0 0 0 0
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0 1
WE_
The cursor is incremented by one and shifted to the right.
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:
0
1
WELCOME_
Write " E ".
The cursor is incremented by one and shifted to the right. Set mode for display shift when writing
0
0
0
1
1
1
WELCOME_
0
0
ELCOME _
Write "
"(space).
The cursor is incremented by one and shifted to the right. Write " C ".
1
1
LCOME C_
The cursor is incremented by one and shifted to the right.
:
:
0
1
COMPAMY_
Write " Y ".
The cursor is incremented by one and shifted to the right. Only shift the cursor's position to the left (Y).
1
0
0
X
X
COMPAMY_
1
0
0
X
X
COMPAMY_
Only shift the cursor's position to the left (M).
OMPANY_
Write " N ".
1
0
The display moves to the left.
1
1
1
X
X
COMPAMY_
Shift the display and the cursor's position to the right.
18
Cursor or display shift
0 0 0 0 0 1 0 1 X X
OMPANY_
Shift the display and the cursor's position to the right.
19
Write data to CG RAM / DD RAM
1 0 0 1 0 0 0 0 0 0
COMPAMY_
Write "
" (space).
The cursor is incremented by one and shifted to the right. : Both the display and the cursor return to the original position (address 0).
20 21 Return home
0 0 0 0 0
:
0 0 0 1 0
:
WELCOME_
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5.5. 4-Bit Operation and 8-Digit 1-Line Display (Using Internal Reset)
No. 1 2 Power on. (SPLC783A starts initializing) Function set
RS R/W DB7 DB6 DB5 DB4 0 0
0 0
Instruction
Display Power on reset. No display. Set to 4-bit operation.
Operation
0
0 0
0
0 0
1
1 X
0
0 X
3
0 0
Set to 4-bit operation and select 1-line display line and character font.
4
0 0
0 0 0 0
0 1 0 0
0 1 0 1
0 1 0 1
0
_
0 0 0
Display on. Cursor appears. Increase address by one.
5
0 0
_
It will shift the cursor to the right when writing to the DD RAM / CG RAM. Now the display has no shift. Write " W ".
6
1 1
0 0
0 0
5.6. 8-Bit Operation and 8-Digit 2-Line Display (Using Internal Reset)
No. 1 2 Power on. Function set
0 0 0
(SPLC783A starts initializing)
RS R/W DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 0 1 1 1 0 X X
3
Display on / off control
0 0 0 0 0
4
Entry mode set
0 0 0
5
Write data to CG RAM / DD RAM
1 0 0 1 0 1 0 1
6 7
Write data to CG RAM / DD RAM
1 0 0 1 0 0 0 1
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1 1 0 1 1 1
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The cursor is incremented by one and shifted to the right.
Instruction
Display
Operation
Power on reset. No display.
Set to 8-bit operation and select 2-line display line and 5 x 8 dot
character font. Display on.
_
0
1
1
1
0
Cursor appear.
Increase address by one. CG RAM.
0
0
0
0
1
1
0
_
It will shift the cursor to the right when writing to the DD RAM / Now the display has no shift. Write " W ".
W_
1
1
The cursor is incremented by one and shifted to the right. :
:
:
WELCOME_
Write " E ".
0
1
The cursor is incremented by one and shifted to the right.
WELCOME _
8
Set DD RAM address
0 0 1 1 0 0 0 0 0 0
It sets DD RAM's address. The cursor is moved to the beginning position of the 2nd line. Write " T ". The cursor is incremented by one and shifted to the right. : Write " T ". The cursor is incremented by one and shifted to the right.
9
Write data to CG RAM / DD RAM
1 0 0 1 0 1 0 1 0 0
WELCOME T_
10 11
: Write data to CG RAM / DD RAM
1 0 0 1 0 1 0 1 0 0
:
WELCOME TO PART_
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SPLC783A
No. 12 Entry mode set
0 0 0 0 0 0 0 1 1 1
Instruction
Display
WELCOME TO PART_
Operation When writing, it sets mode for the display shift.
13
Write data to CG RAM / DD RAM
1 0 0 1 0 1 1 0 0 1
ELCOME O PARTY_
Write " Y ". The cursor is incremented by one and shifted to the right. : Both the display and the cursor return to the original position (address 0).
14 15 Return home
0 0 0 0 0
:
:
WELCOME TO PARTY
0
0
0
1
0
5.7. RESET Function
follows:
At power on, SPLC783A starts the internal auto-reset circuit and executes the initial instructions. The initial procedures are shown as
RS R/W DB7 DB6 DB5 DB4 DB3 DB3 DB1 DB0 00 0 0 1 1 X X X X
RS R/W DB7 DB6 DB5 DB4 DB3 DB3 DB1 DB0 00 0 0 1 1 X X X X
RS R/W DB7 DB6 DB5 DB4 DB3 DB3 DB1 DB0 00 0 0 1 1 X X X X
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[ 8-Bit Interface ] Power On W ait time > 15 ms after VDD > 4.5V
W ait time > 40ms After VDD > 2.7V
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BF cannot be checked before this instruction . Function set ( Interface is 8 bits length . )
W ait time > 4.1 ms
BF cannot be checked before this instruction . Function set ( Interface is 8 bits length . )
W ait time > 100 us
BF cannot be checked before this instruction . Function set ( Interface is 8 bits length . )
BF can be checked after the following instructions .
RS R/W DB7 DB6 DB5 DB4 DB3 DB3 DB1 DB0 0 0 0 0 1 1 N F X X 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 1 0 0 I/D 0 1 S
Function set ( Interface is 8 bits length . Specify the number of display lines and character font . ) The number of display lines and character font cannot be changed afterwards . Display off Display clear
Initialization Ends
Entry mode set
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SPLC783A
[ 4-Bit Interface ] Power On
W ait time > 15 ms after VDD > 4.5V
W ait time > 40ms After VDD > 2.7V
RS R/W DB7 DB6 DB5 DB4 0 0 0 0 1 1
BF cannot be checked before this instruction . Function set ( Interface is 8 bits length . )
W ait time > 4.1 ms
RS R/W DB7 DB6 DB5 DB4 0 0 0 0 1 1
BF cannot be checked before this instruction . Function set ( Interface is 8 bits length . )
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RS R/W DB7 DB6 DB5 DB4 0 0 0 0 1 1 Function set ( Interface is 8 bits length . ) RS R/W DB7 DB6 DB5 DB4 0 0 0 0 1 0 0 0 0 0 1 0 0 0 N 1 F X 0 X 0 BF can be checked after the following instructions . 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Function set ( Interface is 4 bits length . Specify the number of the display lines and character font . ) 0 0 0 0 1 The number of display lines and character font cannot be changed afterwards . Display off 0 0 0 0 1 I/D S Display clear Initialization Ends Entry mode set
W ait time > 100 us
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BF cannot be checked before this instruction .
Function set ( Set interface to be 4 bits length) Interface is 8 bits length .
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5.8. Display Data RAM (DD RAM)
The 80-bit DD RAM is normally used for storing display data. Those DD RAM not used for display data can be used as general data RAM. Its address is configured in the Address Counter. The relationships between Display Data RAM Address and LCDs position are depicted as follows.
1-line display , 80 display characters 1 2 3 4 5 6 00 01 02 03 04 05
79 4E
80 4F
Display position Display data RAM address
( Example ) 1-line display , 8 display characters 1 2 3 4 5 6 7 8 00 01 02 03 04 05 06 07
Display position Display data RAM address
When the display shift operation is performed , the display data RAM's address moves as : ( i ) Left shift 01 ( ii ) Right shift 4F 00
5.9. Timing Generation Circuit
the internal circuits.
The timing generating circuit is able to generate timing signals to
interface, the MPU access timing and the RAM access timing are generated independently.
5.10. LCD Driver Circuit
the LCD driver circuit.
Total of 16 commons and 80 segments signal drivers are valid in When a program specifies the character fonts and line numbers, the corresponding common signals output drive-waveforms and the others still output unselected waveforms.
id se f nU o C ER sN lu I pM nT uR SA P r o F
02 03 04 05 06 06 07 08 01 02 03 04
In order to prevent the internal timing dots character patterns. generator RAM through program.
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It also
06
5.11. Character Generator ROM (CG ROM)
Using 8-bit character code, the character generator ROM generates 5 x 8 dots or 5 x 10 dots character patterns. can generate 192's 5 x 8 dots character patterns and 64's 5 x 10
5.12. Character Generator RAM (CG RAM)
Users can easily change the character patterns in the character It can be written to 5 x 8 dots, 8-character patterns or 5 x 10 dots for 4-character patterns.
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The following diagram shows the SPLC783A character patterns: Correspondence between Character Codes and Character Patterns.
Higher 4-bit (D4 to D7) of Character Code (Hexadecimal) 0 CG RAM (1) 1 2 3 4 5 6 7 8 9 A B C D E F
0
1
CG RAM (2) CG RAM (3) CG RAM (4) CG RAM (5) CG RAM (6) CG RAM (7) CG RAM (8) CG RAM (1) CG RAM (2) CG RAM (3) CG RAM (4) CG RAM (5) CG RAM (6) CG RAM (7) CG RAM (8)
2
3
4
5 Lower 4-bit (D0 to D3) of Character Code (Hexadecimal)
6
7
8
9
A
B
C
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D
E
F
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The relationships between Character Generator RAM Addresses, Character Generator RAM Data (character patterns), and Character Codes are depicted as follows: 1. 5 x 8 dot character patterns
Character Code ( DD RAM Data ) b7 b6 b5 b4 b3 b2 b1 b0
CG RAM Address b5 b4 b3 b2 b1 b0 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 X
Character Patterns ( CG RAM Data ) b7 b6 b5 b4 b3 b2 b1 b0 1 0 0 X X 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 1 0 0 0 0 0 1 0 1 1 1 1 1 1 1 0 1 1 1 1 1 1 1 0 1 0 0 0 0 0 0 0 1 0 0 0 0 0 1 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
0
0
0
0
X
0
0
0
0
0
0
0
0
0
Note1: Note2:
It means that the bit0~2 of the character code correspond to the bit3~5 of the CG RAM address. These areas are not used for display, but can be used for the general data RAM.
Note3: When all of the bit4-7 of the character code are 0, CG RAM character patterns are selected. Note4: " 1 ": Selected , " 0 " : No selected , " X " : Do not care (0 or 1). display " T " character. with the cursor.
Note5: For example (1), set character code (b2 = b1 = b0 = 0, b3 = 0 or 1, b7-b4 = 0) to display " T ". That means character code (00) 16,and (08) 16 can Note6: The bits 0-2 of the character code RAM is the character pattern line position. The 8th line is the cursor position and display is formed by logical OR
nU o C ER sN lu I pM nT uR SA P r o F
0 X 0 0 1 0 0 1 X X X
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Character Pattern Example (1)
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Cursor Position
Character Pattern Example (2)
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2). 5 X 10 dot character patterns
Character Code ( DD RAM Data ) b7 b6 b5 b4 b3 b2 b1 b0
CG RAM Address b5 b4 b3 b2 b1 b0 0 0 0 0 0 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 X
Character Patterns ( CG RAM Data ) b7 b6 b5 b4 b3 b2 b1 b0 1 1 1 1 1 X X 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 1 0 1 1 1 1 1 1 1 1 1 1 0 Character Pattern Example (1)
0
0
0
0
X
0
0
X
0
0
0 0 0 1 1 1 1 1 1 1 1
Note1: Note2:
It means that the bit1~2 of the character code correspond to the bit4~5 of the CG RAM address. These areas are not used for display, but can be used for the general data RAM.
Note3: When all of the bit4-7 of the character code are 0, CG RAM character patterns are selected. Note4: " 1 ": Selected, " 0 ": No selected, " X ": Do not care (0 or 1). (08) 16,and (09) 16 can display " U " character. with the cursor.
Note5: For example (1), set character code (b2 = b1 = 0, b3 = b0 = 0 or 1, b7-b4 = 0) to display " U ". That means all of the character codes (00) 16, (01) 16, Note6: The bits 0-3 of the character code RAM is the character pattern line position. The 11th line is the cursor position and display is formed by logical OR
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X X X X X X X X
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Cursor Position
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5.13. Cursor/Blink Control Circuit
This circuit generates the cursor or blink in the cursor / blink control circuit. The cursor or the blink appears in the digit at the Display Data RAM Address defined in the Address Counter. When the Address Counter is (07) 16, the cursor position is shown as belows:
b6 AC 0
b5 0
b4 0
b3 0
b2 1
b1 1
b0 1
In a 1-line display digit 1 00 2 01 3 02 4 03 5 04 6 05 7 06 8 07 9 08 10 09
Display position
In a 2-line display digit 1st line 2nd line
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1 2 3 4 5 6 7 8 9 10 Display position 00 40 01 41 02 42 03 43 04 44 05 45 06 46 07 47 08 48 09 49 ( Hexadecimal ) the cursor position
the cursor position
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Display data RAM address ( Hexadecimal )
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Display data RAM address
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5.14. Interfacing to MPU
There are two types of data operations: 4-bit and 8-bit operations. Using 4-bit MPU, the interfacing 4-bit data is transferred by 4-busline (DB4 to DB7). used. transferring. Thus, DB0 to DB3 bus lines are not Using 4-bit MPU to interface 8-bit data requires two times First, the higher 4-bit data is transferred by 4-busline (for 8-bit operation, DB7 to DB4). DB0). Secondly, the lower 4-bit data is transferred by 4-busline (for 8-bit operation, DB3 to For 8-bit MPU, the 8-bit data is transferred by 8-buslines (DB0 to DB7).
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Example of 4-bit Data Transfer Timing Sequence
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5.15. Supply Voltage for LCD Drive
Different voltages can be supplied to SPLC783A's pins (V5 - 1) for obtaining LCD drive-waveform. factor and supply voltages are shown as belows:
Supply Voltage
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Example of 8-bit Data Transfer Timing Sequence
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The relationships between bias, duty
Duty Factor
1/8, 1/11 1/4
1/16 1/5
V1 V2 V3 V4 V5
VDD - 1/4 VLCD VDD - 1/2 VLCD VDD - 1/2 VLCD VDD - 3/4 VLCD VDD - VLCD
VDD - 1/5 VLCD VDD - 2/5 VLCD VDD - 3/5 VLCD VDD - 4/5 VLCD VDD - VLCD
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5.15.1. The power connections for LCD (1/4 Bias, 1/5 Bias) are shown belows:
VDD ( +5.0V ) VDD R V1 R V LCD V3 R V3 V1 R VDD ( +5.0V )
VDD R
V2
V2
V4 R V5
V4
The bypass-capacitor improves the LCD display quality.
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V5 VR VR 1 / 4 Bias 1 / 5 Bias (1/8,1/11 Duty) -V or Gnd (1/16 Duty) -V or Gnd
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V LCD
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VDD ( +5.0V )
VDD ( +5.0V )
VDD
VDD
R
C
R
C
V1
V1
V2
R
R
C
C
V2
R
V3
R
V3
C
C
R
V4
C
V4
R
C
R
C
V5
V5
VR 1 / 4 Bias (1/8,1/11 Duty) -V or Gnd 1 / 5 Bias (1/16 Duty)
VR
-V or Gnd
The bias voltage must have the following relations: VDD V1 V2 V3 V4 V5.
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5.15.2. The relationship between LCD frames frequency and oscillators frequency.
(Assume the oscillation frequency is 250KHz, 1 clock cycle time = 4.0s)
5.15.2.1. 1/8 duty, TYPE-B waveform
400 clocks 12 VDD V1 COM1 V2(V3) V4 V5 1 Frame 1 Frame 7812 7812 7812 78
5.15.2.2. 1/11 duty, TYPE-B waveform
5.15.2.3. 1/16 duty, TYPE-B waveform
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400 clocks 12 10 11 1 2 10 11 1 2 VDD V1 COM1 V2(V3) V4 V5 1 Frame 1 Frame 1 frame = 4(s) x 400 x 11 = 17600(s) = 17.6ms Frame frequency 1 17.6(ms) 5 6 .8(Hz)
1 frame = 4(s) x 400 x 8 = 12800(s) = 12.8ms 1 Frame frequency 78.1(Hz) 12.8(ms)
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200 clocks
12
15 16 1 2
15 16 1 2
VDD V1 COM1 V2 V3 V4 V5
1 Frame 1 frame = 4(s) x 200 x 16 = 12800(s) = 12.8ms 1 Frame frequency 78.1(Hz) 12.8(ms)
1 Frame
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5.16. REGISTER --- IR (Instruction Register) and DR (Data Register)
SPLC783A contains two 8-bit registers: Instruction Register (IR) and Data Register (DR). Using combinations of the RS pin and the R/W pin selects the IR and DR, see below:
5.19. I/O Port Configuration 5.19.1. Input port: E
VDD
PMOS
RS 0 0 1 1
R/W 0 1 0 1
Operation IR write (Display clear, etc.) Read busy flag (DB7) and Address Counter (DB0 - DB6) DR write (DR to Display data RAM or Character generator RAM) DR read (Display data RAM or Character generator RAM to DR)
NMOS
5.19.2. Input port: R / W, RS
The IR can be written by MPU, but it cannot be read by MPU.
5.17. Busy Flag (BF)
When RS = 0 and R/W = 1, the busy flag is output to DB7. any instruction until the busy flag = 0.
the busy flag =1, SPLC783A is in busy state and does not accept
5.18. Address Counter (AC)
and Character Generator RAM.
The Address Counter assigns addresses to Display Data RAM
is written in IR, the address information is sent from IR to AC. Generator RAM, AC is automatically incremented by one (or decremented by one). DB6 when RS = 0 and R/W = 1.
After writing to/reading from Display Data RAM or Character The contents of AC are output to DB0 -
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As
VDD PMOS
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NMOS
5.19.3. Output port: CLK1, CLK2, M, D
When an instruction for address
NMOS
5.19.4. Input / Output port: DB7 - 0
VDD VDD VDD
Enable
PMOS
PMOS
NMOS
Data
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6. ELECTRICAL SPECIFICATIONS
6.1. Absolute Maximum Ratings
Characteristics Operating Voltage Driver Supply Voltage Input Voltage Range Operating Temperature Storage Temperature
conditions see AC/DC Electrical Characteristics.
Symbol VDD VLCD VIN TA TSTO
Ratings -0.3V to +7.0V VDD - 12V to VDD + 0.3V -0.3V to VDD + 0.3V -30 to +80 -55 to +125
Note: Stresses beyond those given in the Absolute Maximum Rating table may cause operational errors or damage to the device.
6.2. DC Characteristics (VDD = 2.7V to 4.5V, TA = 25)
Characteristics Operating Current Symbol IDD Limit Min. Typ. 0.2 Max. 0.4
Input High Voltage Input Low Voltage
Input High Voltage Input Low Voltage
Input High Current Input Low Current Output High Voltage (TTL) Output Low Voltage (TTL) Output High Output Low
Voltage (CMOS) Voltage (CMOS) (COM) (SEG) LCD Voltage
Driver ON Resistance Driver ON Resistance
Note: FOSC = 270KHz, VDD = 3.0V, pin E = "L", RS, R/W, DB0 - DB7 are open, all outputs are no loads.
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mA V VIH1 VIL1 0.7VDD -0.3 VDD 0.4 V VIH2 VIL2 IIH IIL 0.7VDD -0.2 VDD V 0.2VDD 1.0 V Pin OSC1 -1.0 -5.0 2.0 A -15 -30 A V V V V VOH1 VOL1 0.2VDD VOH2 VOL2 0.8VDD 0.2VDD 10 15 11 RCOM RSEG VLCD K K V 3.0
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For normal operational
Test Condition
External clock (Note) Pins:(E, RS, R/W, DB0 - DB7)
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Pins: (RS, R/W, DB0 - DB7) VDD = 3.0V IOH = - 0.1mA IOL = 0.1mA IOH = - 40A, IOL = 40A, Pins: IO = 50A, VLCD = 4.0V
Pins: DB0 - DB7 Pins: DB0 - DB7
Pins: CLK1, CLK2, M, D CLK1, CLK2, M, D Pins: COM1 - COM16 Pins: SEG1 - SEG80 VDD-V5, 1/4 bias or 1/5 bias
IO = 50A, VLCD = 4.0V
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6.3. AC Characteristics (VDD = 2.7V to 4.5V, TA = 25) 6.3.1. Internal clock operation
Characteristics OSC Frequency Symbol FOSC1 Limit Min. 190 Typ. 270 Max. 350 Unit KHz Test Condition VDD = 3.0V, Rf = 75K2%
6.3.2. External clock operation
Characteristics External Frequency Duty Cycle Rise/Fall Time tr, tf Symbol FOSC2 Limit Min. 125 45 Typ. 250 50 Max. 350 55 0.2 Unit KHz % s
6.3.3. Write mode (Writing data from MPU to SPLC783A)
Characteristics E Cycle Time E Pulse Width Symbol tC
E Rise/Fall Time
Address Setup Time Address Hold Time Data Setup Time Data Hold Time
6.3.4. Read mode (Reading data from SPLC783A to MPU)
Characteristics E Cycle Time E Pulse Width Symbol tC
E Rise/Fall Time
Address Setup Time Address Hold Time
Data Output Delay Time Data hold time
id se f nU o C ER sN lu I pM nT uR SA P r o F
Limit Typ. Min. Max. Unit ns 1400 400 Pin E tPW ns ns ns ns Pin E Pin E t R, t F tSP1 25 60 tHD1 tSP2 20 140 10 ns tHD2 ns Limit Typ. Min. Max. Unit ns ns 1400 400 Pin E Pin E tW t R, t F tSP1 25 ns Pin E 60 ns ns tHD1 tD 20 360 ns tHD2 5.0 ns
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Test Condition
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Test Condition
Pins: RS, R/W, E Pins: RS, R/W, E
Pins: DB0 - DB7 Pins: DB0 - DB7
Test Condition
Pins: RS, R/W, E Pins: RS, R/W, E
Pins: DB0 - DB7 Pin DB0 - DB7
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6.4. DC Characteristics (VDD = 4.5V to 5.5V, TA = 25)
Characteristics Operating Current Input High Voltage Input Low Voltage Input High Voltage Input Low Voltage Input High Current Input Low Current Output High Voltage (TTL) Output Low Voltage (TTL) Output High Output Low Symbol IDD VIH1 VIL1 VIH2 VIL2 IIH IIL VOH1 VOL1 Limit Min. 2.2 -0.3 VDD-1 -0.2 -1.0 -20 2.4 Typ. 0.4 -50 Max. 0.6 VDD 0.6 VDD 1.0 1.0 -100 VDD 0.4 Unit mA V V V V A A Pin OSC1 Pin OSC1 Pins: (RS, R/W, DB0 - DB7) VDD = 5.0V Test Condition External clock (Note) Pins:(E, RS, R/W, DB0 - DB7)
Voltage (CMOS) Voltage (CMOS) (COM) (SEG) LCD Voltage
Driver ON Resistance Driver ON Resistance
Note: FOSC = 270KHz, VDD = 5.0V, pin E = "L", RS, R/W, DB0 - DB7 are open, all outputs are no loads.
6.5. AC Characteristics (VDD = 4.5V to 5.5V, TA = 25) 6.5.1. Internal clock operation
Characteristics OSC Frequency
6.5.2. External clock operation
Characteristics External Frequency Duty Cycle Rise/Fall Time
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V VOH2 VOL2 0.9VDD VDD V IOH = -40A, 0.1VDD 10K V RCOM RSEG VLCD K 15K 11 K V 3.0 Symbol FOSC1 Limit Typ. 270 Min. 190 Max. 350 Unit KHz Symbol FOSC2 Limit Typ. 250 50 Min. 125 45 tr, tf Max. 350 55 0.2 Unit KHz % s
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IOH = -0.205mA
Pins: DB0 - DB7 IOL = 1.2mA Pins: DB0 - DB7
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Pins: CLK1, CLK2, M, D IOL = 40A, Pins: CLK1, CLK2, M, D
IO = 50A, VLCD = 4.0V Pins: COM1 - COM16 Pins: SEG1 - SEG80
IO = 50A, VLCD = 4.0V
VDD-V5, 1/4 bias or 1/5 bias
Test Condition
VDD = 5.0V, Rf = 91K2%
Test Condition
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6.5.3. Write mode (Writing Data from MPU to SPLC783A)
Characteristics E Cycle Time E Pulse Width E Rise/Fall Time Address Setup Time Address Hold Time Data Setup Time Data Hold Time Symbol tC tPW t R, t F tSP1 tHD1 tSP2 tHD2 Limit Min. 500 220 40 10 60 10 Typ. Max. 25 Unit ns ns ns ns ns ns ns Pin E Pin E Pin E Pins: RS, R/W, E Pins: RS, R/W, E Pins: DB0 - DB7 Pins: DB0 - DB7 Test Condition
6.5.4. Read mode (Reading Data from SPLC783A to MPU)
Characteristics E Cycle Time E Pulse Width Symbol tC Limit Min. 500 220 Typ. Max. -
E Rise/Fall Time
Address Setup Time Address Hold Time
Data Output Delay Time Data hold time
6.5.5. Interface mode with LCD Driver (SPLC100A1)
Characteristics Symbol tPWH tPWL tCSP
Clock pulse width high Clock pulse width low Clock setup time Data setup time Data hold time M delay time
id se f nU o C ER sN lu I pM nT uR SA P r o F
ns ns ns Pin E Pin E Pin E tW t R, t F tSP1 25 40 10 ns ns tHD1 tD 120 ns tHD2 20 ns Limit Typ. Min. 800 Max. Unit ns 800 500 300 300 ns ns ns ns tDSP tHD tD Pins: D Pins: D -1000 1000 ns Pins: M
Unit
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Test Condition
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Pins: RS, R/W, E Pins: RS, R/W, E
Pins: DB0 - DB7 Pin DB0 - DB7
Test Condition
Pins: CLK1, CLK2 Pins: CLK1, CLK2 Pins: CLK1, CLK2
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6.5.6. Write mode timing diagram (Writing Data from MPU to SPLC783A)
RS
VIH1 VIL1 t SP1 VIL1 tPW VIH1 VIL1 tR VIH1 VIL1 VIH1 VIL1 t SP2 Valid Data tC
VIH1 VIL1 t
HD1
R/W
VIL1 tF t
HD1
E
t HD2
DB7 - 0
VIH1 VIL1
6.5.7. Read mode timing diagram (Reading Data from SPLC783A to MPU)
RS
R/W
DB7 - 0
6.5.8. Interface mode with SPLC100A1 timing diagram
CL1
0.9VDD
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VIH1 VIL1 t SP1 VIH1 VIL1 t HD1 VIH1 VIH1 tPW
E
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VIH1 VIL1
VIH1 VIL1
tF t HD1
VIL1
tR
tD VIH1 VIL1
Valid Data tC
t HD2
VIH1 VIL1
tPWH
0.9VDD
tPWH
CL2
t CSP
0.1VDD 0.1VDD
0.9VDD
t
D
CSP
tPWL
0.9VDD 0.1VDD 0.9VDD 0.1VDD
t DSP
M
0.1VDD
t
HD
tD
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7. APPLICATION CIRCUITS
7.1. R-Oscillator
The oscillation resistor Rf is used only for the internal oscillaotr operation mode.
OSC1 Rf : 75K 2% ( when VDD = 3.0V) Rf : 91K 2% ( when VDD = 5.0V) Since the oscillation frequency varies depending on the OSC1 and OSC2 pin capacitance, the wiring length to these pins should be minimized.
OSC2
400 Fosc ( KHz )
600
Fosc ( KHz )
270 200
400 270 200
7.2. Interface to MPU
7.2.1. Interface to 8-bit MPU (6805)
7.2.2. Interface to 8-bit MPU (Z80)
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0 0 75 100 200 300 400 0 Rosc ( Kohms ) 0 91 100 200 300 Rosc ( Kohms )
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VDD = 3.0V
VDD = 5.0V
PA0 | PA7
8
DB0 | DB7
COM1 | COM16
16
LCD PANEL
6805
SPLC783A
16 COMMONS X
PB0
E
PB1 PB2
RS
R/W
SEG1 | SEG80
80
80 SEGMENTS
D0 | D7 Z80 A1 | A7 A0 IO RQ WR 7
8
DB0 | DB7 E RS R/W
CO M 1 | CO M 16
16
LCD PANEL 16 CO MM O NS X
SPLC783A SEG 1 | SEG 80 80
80 SEG M ENTS
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7.3. SPLC783A Application Circuit
DOT MATRIX LCD PANEL
16 (8)
COM16 (COM8) | COM1
80
SEG80 | SEG1
40
Y1-Y40 DL1 VDD FCS SHL1 SHL2 GND VEE
SPLC100A1
DR2 DL2 DR1 CLK1 CLK2 M DL1 VDD FCS SHL1 SHL2 GND VEE
40
Y1-Y40
SPLC100A1
DR2 DL2 DR1 CLK1 CLK2 M DL1 VDD FCS SHL1 SHL2 GND VEE
40
Y1-Y40
SPLC100A1
DR2
VDD GND CLK1 CLK2 M V1 V2 V3 V4 V5
SPLC783A
VDD ( +5.0V )
7.4. Applications for LCD
SPLC783A COM1
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R R R R R V R C C C C C -V or Gnd
( Example 1 ) : 5 x 8 dots , 16 characters x 1 line [ 1 / 4 Bias , 1 / 8 Duty ]
V1 V2 V3 V4 V5 V6
V1 V2 V3 V4 V5 V6
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DL2 DR1
CLK1 CLK2 M
V1 V2 V3 V4 V5 V6
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LCD Panel
COM8 SEG1
16 characters x 1 line
SEG80
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SPLC783A COM1 LCD Panel 16 characters x 1 line COM11 SEG1
SEG80 ( Example 2 ) : 5 x 10 dots , 16 characters x 1 line [ 1 / 4 Bias , 1 / 11 Duty ]
SPLC783A COM1
COM8 COM9
COM16 SEG1
SEG80
SPLC783A COM1
COM8 SEG1
SEG80 COM9
id se f nU o C ER sN lu I pM nT uR SA P r o F
( Example 3 ) : 5 x 8 dots , 16 characters x 2 lines [ 1 / 5 Bias , 1 / 16 Duty ]
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LCD Panel
16 characters x 2 lines
COM16 ( Example 4 ) : 5 x 8 dots , 32 characters x 1 line [ 1 / 5 Bias , 1 / 16 Duty ]
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SPLC783A
SEG1 SEG40 COM1 LCD Panel COM8
SEG41 SEG80
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( Example 5 ) : 5 x 8 dots , 8 characters x 2 lines [ 1 / 4 Bias , 1 / 8 Duty ]
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8. CHARACTER GENERATOR ROM
8.1. SPLC783A - 001
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8.2. SPLC783A - 003
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9. PACKAGE/PAD LOCATIONS
9.1. PAD Assignment and Locations
Please contact Sunplus sales representatives for more information.
9.2. Package Information
D D1
Symbol
A A1 A2 D D1 E E1 e b c L1
Unit: Millimeter
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E E1 c A2 A A1
L1
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Min.
Nom.
Max.
-
-
1.60 0.15 1.45 22.10 20.10 16.10 14.10 0.27 0.20
0.05 1.35
1.40
21.90 15.90 13.90 0.17 0.09
22.00 16.00 14.00 0.22 -
19.90
20.00
0.50 BSC.
1.00 REF
9.3. Ordering Information
Product Number SPLC783A-NnnV-C SPLC783A-NnnV-PL11 SPLC783A-NnnV-HL11
Note1: Code number is assigned for customer. Note2: Code number (N = A - Z or 0 - 9, nn = 00 - 99); version (V = A - Z).
Package Type Chip form Package form - LQFP 128* Green Package form - LQFP 128**
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9.4. Storage Condition and Period for Package
Package *LQFP **LQFP Moisture sensitivity level LEVEL 3 LEVEL 3 Max. Reflow temperature 220 +5/-0 255 +5/-0 Floor life storage condition 168Hrs @ 30/ 60% R.H. 168Hrs @ 30/ 60% R.H. Dry pack Yes Yes
Note1: Please refer to IPC/JEDEC standard J-STD-020A and EIA JEDEC stand JFSD22-A112 Note2: or refer to the "CAUTION Note" on dry pack bag.
9.5. Recommended SMT Temperature Profile
This "Recommended" temperature profile is a rough guideline for SMT process reference. Most of SUNPLUS leadframe base product choice Matte Tin and Sn/Bi for plating recipe. For PPF(Pre-Plated Frame) product with 63/37 solder paste, we recommend 240~245 for peak temperature.
id se f nU o C ER sN lu I pM nT uR SA P r o F
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10. DISCLAIMER
The information appearing in this publication is believed to be accurate. Integrated circuits sold by Sunplus Technology are covered by the warranty and patent indemnification provisions stipulated in the terms of sale only. SUNPLUS makes no warranty, express, statutory implied or by description regarding the information in this publication or FURTHER, SUNPLUS MAKES NO WARRANTY OF SUNPLUS reserves the right to halt production or alter the specifications and regarding the freedom of the described chip(s) from patent infringement. MERCHANTABILITY OR FITNESS FOR ANY PURPOSE. prices at any time without notice. publication are current before placing orders.
Accordingly, the reader is cautioned to verify that the data sheets and other information in this Products described herein are intended for use in normal commercial applications. Please note that application circuits
Applications involving unusual environmental or reliability requirements, e.g. military equipment or medical life support equipment, are specifically not recommended without additional processing by SUNPLUS for such applications. illustrated in this document are for reference purposes only.
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11. REVISION HISTORY
Date MAR. 10, 2005 Revision # 1.4 Description 1. Modify 8.1 and 8.2 code numbers from 2 digits to 3 digits 2. Add Green Package Product Number 3. Add sections 9.4 and 9.5 4. Correct pin name: from RW to R/W Page 33, 34 35 36 5, 9 19, 20 APR. 01, 2004 1.3 1. Add min. and max. value in Instruction Table 2. Add 8-bit/4-bit data transfer timing sequence example NOV. 25, 2003 1.2 1. Add package information: LQFP 128 pin 2. Remove "9. PACKAGE/PAD LOCATIONS" SEP. 27, 2002 OCT. 02, 2001 1.1 1.0 Correct "9. PACKAGE/PAD LOCATIONS" Original
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19 - 20 5, 6, 34 31 - 33
9
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